Semiconductor device of multi-wiring structure and method of manufacturing the same

ABSTRACT

A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2001-298309, filed Sep.27, 2001, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device of amulti-wiring structure, particularly, to the structure of an insulatingfilm within the same wiring layer.

[0004] 2. Description of the Related Art

[0005] In order to improve the performance of a semiconductor device,particularly, an LSI, the dielectric constant of the insulating filmused in the multi-wiring structure is being made lower and lower. To bemore specific, by lowering the dielectric constant of the insulatingfilm formed between adjacent wiring layers, the parasitic capacitancebetween the adjacent wiring layers is lowered, and the delay time of thesignal propagated through the wiring is improved so as to improve theoperation speed of the LSI.

[0006] In order to lower the dielectric constant k of the insulatingfilm to 3 or less, it is necessary to lower the density of theinsulating film. However, because of the trade off relationship with themechanical strength of the insulating film, the mechanical strength ofthe insulating film is rendered insufficient with decrease in thedielectric constant of the insulating film.

[0007] In the semiconductor device of the conventional multi-wiringstructure, the insulating film used in the same wiring layer is formedof a single material. If the insulating film is formed of a materialhaving a low dielectric constant, problems are generated as follows.

[0008] First of all, in the case of using an insulating film having alow dielectric constant in the multi-wiring structure, the insulatingfilm is incapable of withstanding the mechanical impact in, for example,the bonding step and the packaging step, leading to breakage of theinsulating film.

[0009] For example, FIG. 1 shows the case where the insulating film isbroken by the mechanical impact in the bonding step. In FIG. 1, each ofa plurality of wiring layers 60 is formed by using an insulating film 61having a low dielectric constant and a low density. Each of a pluralityof metal wirings 62 is formed of, for example, a Cu layer buried in thesurface region of each of the insulating films 61. Also, a bonding pad63 formed of Cu is formed in the uppermost wiring layer 60 together withthe metal wirings 62. Further, a passivation film 64 is formed on theuppermost wiring layer 60.

[0010] It should be noted that, if the insulating film 61 is formed of amaterial having a low dielectric constant and a low density, theinsulating film 61 is broken in the corner portion below the bonding pad63 by the mechanical impact in the bonding step of the bonding pad 63.

[0011] A second problem is that the semiconductor device is adverselyaffected by the gas or water generated from the insulating film in theprocess of forming the insulating film. Where the insulating film isformed by the coating of methyl polysiloxane, followed by baking thecoated film, the coated film of methyl polysiloxane is crosslinked bythe dehydration condensation reaction, with the result that a largeamount of hydrogen and water are released in the process of forming theinsulating film. It should be noted in this connection that, if aferroelectric memory cell or a MIM (metal-insulator-metal) capacitor isformed in the LSI, the capacitor insulating films of these elementsincur deterioration of the performance if heated under a hydrogenatmosphere.

[0012]FIGS. 2A to 2C are cross sectional views collectively showing themanufacturing process of a semiconductor device in which an MIMcapacitor is formed in a single wiring layer forming a multi-wiringstructure.

[0013] In the first step, formed is a wiring layer 60 in which a metalwiring 62 made of, for example, Cu is buried in a surface region of aninsulating film 61 made of, for example, SOG (spin on glass), as shownin FIG. 2A. Then, a stopper insulating film 65 made of, for example,silicon nitride (SiN) is formed on the entire surface, followed byforming an MIM capacitor 66 on the stopper insulating film 65. The MIMcapacitor 66 includes an upper electrode, a lower electrode, and acapacitor insulating film interposed between the upper electrode and thelower electrode and made of, for example, silicon nitride, tantalumoxide or titanium nitride.

[0014] In the next step, the entire surface is coated with, for example,methyl polysiloxane, followed by baking the coated film so as to form aninsulating film 61 constituting the upper wiring layer, as shown in FIG.2B. When the insulating film 61 is baked, a large amount of hydrogen (H)is released from the coated film of methyl polysiloxane. If the releasedhydrogen is heated, hydrogen is taken into the capacitor insulating filmof the MIM capacitor 66 so as to deteriorate the performance.

[0015] Further, a metal wiring 62 made of, for example, Cu is formed ina manner to extend through the surface and the inner region of theinsulating film 61, as shown in FIG. 2C.

[0016] Further, a third problem to be noted is that corrosion, erosionand peeling of another film is caused by the gas released from theinsulating film. There is an insulating film having a highsusceptibility to water and a high water permeability. Also, when itcomes to an insulating film having a bond relatively low in its bondingenergy, there is an unstable film that releases a gas under thetemperature of about 350 to 400° C. in the step of forming amulti-wiring structure. Need less to say, the characteristics of theinsulating film itself that releases the gas are changed. In addition,the corrosion, erosion, and peeling of another insulating film arebrought about by the released gas.

[0017]FIG. 3 shows the peeling of a film in the heating step in the caseof using a film that is likely to release a gas as the insulating film61 constituting a wiring layer. In FIG. 3, the stopper film 65 made of,for example, silicon nitride (SiN) is formed on the insulating film 61constituting the wiring layer, followed by forming a new insulating film61 on the stopper insulating film 65. If the new insulating film 61 isformed of a film that is likely to release a gas in the heating step forbaking the insulating film 61, a gas is released from the insulatingfilm 61. The released gas causes the peeling of the stopper film 65 inthe portion where the bonding strength of the stopper film 65 with theunderlying film is low, e.g., on the bonding pad 63.

[0018] As described above, it was customary in the past to use a singlematerial for forming an insulating film included in the same wiringlayer. Therefore, if it is intended to increase the operating speed byusing an insulating film having a low dielectric constant, seriousproblems are generated in respect of the reliability that the insulatingfilm is broken by a mechanical impact, that the element is adverselyaffected by the gas or water released from the insulating film, and thatthe corrosion, erosion, and the peeling of the film are brought about bythe gas released from the insulating film.

BRIEF SUMMARY OF THE INVENTION

[0019] According to an aspect of the present invention, there isprovided a semiconductor device of a multi-wiring structure, comprisesan electrode to which is applied a mechanical pressure; a firstinsulating film formed in a region where it is necessary to have a highmechanical strength and having the electrode formed therein; a secondinsulating film formed in the same layer as the layer of the firstinsulating film and formed in a region where a mechanical strengthhigher than that of the first insulating layer is not required; and awiring layer formed on the surface of the second insulating film.

[0020] According to another aspect of the present invention, there isprovided a method of manufacturing a semiconductor device having amulti-wiring structure, comprises coating a substrate with a film of aninsulating material in which a crosslinking reaction or a foamingreaction is generated; subjecting the film of the insulating material toa heat treatment so as to bring about a crosslinking reaction or afoaming reaction, thereby forming a first insulating film on thesubstrate; selectively removing the first insulating film such that thefirst insulating film is selectively left unremoved on the substrate andis removed in the other region; and forming a second insulating film inthe region where the first insulating film has been removed.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0021]FIG. 1 is a cross sectional view showing a conventionalsemiconductor device;

[0022]FIGS. 2A to 2C are cross sectional views successively showing theconventional steps of manufacturing a semiconductor device;

[0023]FIG. 3 is a cross sectional view showing a conventionalsemiconductor device;

[0024]FIG. 4A is a plan view showing an LSI chip according to a firstembodiment of the present invention;

[0025]FIG. 4B is a cross sectional view along the line 4B-4B shown inFIG. 4A;

[0026]FIGS. 5A to 5G are cross sectional views successively showing themanufacturing steps of an LSI chip according to the first embodiment ofthe present invention;

[0027]FIGS. 6A and 6B are cross sectional views successively showingother manufacturing steps of an LSI chip according to the firstembodiment of the present invention;

[0028]FIG. 7A is a plan view showing an LSI chip according to a secondembodiment of the present invention;

[0029]FIG. 7B is a cross sectional view along the line 7B-7B shown inFIG. 7A;

[0030]FIGS. 8A to 8F are cross sectional views successively showing themanufacturing steps of an LSI chip according to the second embodiment ofthe present invention;

[0031]FIG. 9A is a plan view showing an LSI chip according to a thirdembodiment of the present invention;

[0032]FIG. 9B is a cross sectional view along the line 9B-9B shown inFIG. 9A;

[0033]FIG. 10 is a plan view showing an LSI chip according to a fourthembodiment of the present invention;

[0034]FIG. 11A is a plan view showing a wiring layer according to amodification of the present invention; and

[0035]FIG. 11B is a cross sectional view along the line 11B-11B shown inFIG. 11A.

DETAILED DESCRIPTION OF THE INVENTION

[0036] Some embodiments of the present invention will now be describedin detail with reference to the accompanying drawings.

[0037]FIGS. 4A and 4B are a plan view and a cross sectional view,respectively, collectively showing an LSI chip according to a firstembodiment of the present invention, in which the technical idea of thepresent invention is applied to an LSI. Incidentally, the constructionin only the upper region of the LSI chip is shown in FIG. 4B. Also, theactual size is not necessarily reflected in the drawings.

[0038] As shown in the drawings, three wiring layers 11, 12 and 13 arelaminated one upon the other in an upper portion of the chip. In each ofthese three wiring layers 11, 12 and 13, two kinds of insulating films,i.e., an insulating film 14 and another insulating film 16, are formedin the central portion and the peripheral portion of the chip,respectively.

[0039] The insulating film 14 formed in the central portion of the chipis formed of, for example, an organic SOD (spin on dielectric) film. Theinsulating film 14 has a large number of pores and has a dielectricconstant k lower than 3. For example, the dielectric constant k of theinsulating film 14 is set to fall within a range of between 2.2 and 2.7.Also, a plurality of metal wirings 15 made of, for example, Cu areburied in a surface region of the insulating film 14.

[0040] The other insulating film 16 formed in the peripheral portion ofthe chip is made of a SiN film formed by, for example, a plasma CVDmethod. The insulating film 16, which has a dielectric constant k higherthan that of the insulating film 14 formed of an organic SOD film, isexcellent in the mechanical strength. A plurality of bonding pads 17made of, for example, Cu are buried in a surface region of theinsulating film 16.

[0041] A stopper film 18 made of at least one material selected from thegroup consisting of SiN, SiCN and SiCO is formed in an upper portion ofeach of the wiring layers 11, 12 and 13. The stopper film 18 serves toprevent Cu from being diffused into another wiring layer.

[0042] It should be noted that the bonding pads 17 formed in the wiringlayers 11, 12 and 13 are electrically connected to each other throughvia wires 19 formed in the wiring layers 12 and 13.

[0043] A passivation film 20 of a three layer structure of, for example,SiN film/TEOS-SiO₂ film/SiN film is formed on the uppermost wiring layer13. An opening 21 for the bonding is formed in that portion of thepassivation film 20 which corresponds to the bonding pad 17.

[0044] In the LSI chip shown in FIGS. 4A and 4B, each of the pluralwiring layers 11, 12 and 13 includes an insulating film having the metalwirings 15 and the bonding pad 17 formed in the surface region. Also,each insulating film includes the insulating film 14 formed in thecentral portion of the chip and the other insulating film 16 formed inthe peripheral portion of the chip.

[0045] The insulating film 14 included in each of the wiring layers 11,12, 13 and having the metal wirings 15 formed in the surface region hasa large number of pores and has a small value of the dielectric constantk falling within a range of between 2.2 and 2.7. Therefore, the degreeof the capacitance coupling between the metal wirings 15 formed in theadjacent metal wiring layers is diminished so as to make it possible tosuppress the value of the parasitic capacitance accompanying each of themetal wirings 15 to a small value. As a result, the delay time of thesignal propagated through each of the metal wirings 15 is improved so asto increase the operating speed of the LSI chip.

[0046] On the other hand, the insulating film 16 positioned around orbelow the bonding pad 17 in each of the wiring layers 11, 12 and 13 ismade of a SiN film formed by a plasma CVD method. The insulating film 16is superior to the insulating film 14 made of an organic SOD film in themechanical strength. Therefore, even where a mechanical impact(mechanical pressure) is applied to the bonding pad 17 in the bondingstep for bonding a wire to the bonding pad 17 included in the uppermostwiring layer 13 or in the packaging step, the insulating film 16 isunlikely to be broken.

[0047] Further, the insulating film 16 consisting of a SiN film formedby a plasma CVD method is low in the water adsorption and in the waterpermeability so as to make it possible to suppress the peeling of thestopper film 18 in the vicinity of the bonding pad 17, in which thepeeling of the film tends to be caused relatively easily by the gasreleased from the insulating film.

[0048] As described above, the LSI chip according to the firstembodiment of the present invention permits achieving a high operatingspeed without impairing the reliability.

[0049] In the first embodiment of the present invention described above,the insulating film constituting each of the wiring layer is formed oftwo different kinds of insulating films. However, it is also possiblefor the insulating film constituting each wiring layer to be formed ofthree or more different kinds of insulating films.

[0050] Also, in the first embodiment described above, an organic SODfilm is used for forming the insulating film 14 having a dielectricconstant not larger than 3. However, some of the SiN films formed by aplasma CVD method have a dielectric constant not larger than 3. It isalso possible to use such a SiN film having a dielectric constant notlarger than 3 for forming the insulating film 14.

[0051] The LSI chip shown in FIGS. 4A and 4B can be manufactured by themanufacturing process described in the following with reference to FIGS.5A to 5G.

[0052] In the first step, an organic SOD (spin on dielectric) film 31 isformed on a wafer (substrate) 30 having elements and other wiring layersformed therein in advance by coating the surface of the wafer 30 with acoating material prepared by mixing an insulating film precursorincluding SiO₂ having an OH group attached thereto as a basic skeletalstructure and a solvent, as shown in FIG. 5A. A spin coating method isemployed for the coating.

[0053] In the next step, a heat treatment is applied to the organic SODfilm 31 under an oxygen gas atmosphere or a nitrogen gas atmosphereunder temperatures of, for example, 350 to 400° C. so as to convert theorganic SOD film 31 into an insulating film 14, as shown in FIG. 5B. Inthis step, a dehydration polymerization takes place between theinsulating film precursors so as to form crosslinkage of SiO₂ with anoxygen atom interposed therebetween. As a result, a large number ofpores are formed in the insulating film 14 so as to render theinsulating film 14 porous.

[0054] In general, the dehydration polymerization is brought about undertemperatures not lower than 350 to 400° C., and evaporation of thesolvent is started at about 200° C. Also, the dielectric constant k ofthe porous insulating film 14 falls within a range of between 2.2 and2.7.

[0055] In the next step, the insulating film 14 is selectively etched bya PEP process so as to leave the insulating film 14 unremoved in thecentral portion alone of each chip and to remove the other portion, asshown in FIG. 5C, followed by depositing an insulating film 16 made ofSiN on the entire surface by, for example, a plasma CVD method, as shownin FIG. 5D.

[0056] Further, the upper portion of the insulating film 16 is removedby the polishing with a CMP method or by an etch back method afterdeposition of a resist until the upper surface of the insulating film 16is rendered flush with the upper surface of the insulating film 14, asshown in FIG. 5E. As a result, formed is an insulating film consistingof the insulating film 14 formed in the central portion of each chip andthe insulating film 16 formed in the peripheral portion of each chip.

[0057] In the next step, a metal wiring 15 is formed in a surface regionof the insulating film 14, and a bonding pad 17 is formed in a surfaceregion of the insulating film 16, as shown in FIG. 5F.

[0058] The metal wiring 15 and the bonding pad 17 are formed as follows.Specifically, grooves for forming the metal wirings and the bonding padare formed in the surface regions of the insulating film 14 and theinsulating film 16, respectively, followed by successively forming, asrequired, a barrier metal layer made of TaN, Ta or WN and a Cu layerused as a seed by a sputtering method. Then, a Cu layer is formed by anelectroplating method, followed by polishing the resultant Cu layer by aCMP method so as to planarize the Cu layer.

[0059] Finally, a stopper layer 18 made of, for example, SiN, SiCN orSiCO is formed on the entire surface, as shown in FIG. 5G.

[0060] A single wiring layer is formed by the series of the processsteps described above, and a multi-layered wiring is formed by repeatingthe desired number of times the series of the process steps describedabove.

[0061] In the embodiment described above, a heat treatment is applied toan organic SOD film so as to bring about a crosslinking reaction and,thus, to form the porous insulating film 14 having a large number ofpores. Alternatively, it is also possible to mix a resin having a highmolecular weight in the SOD film and to apply a heat treatment to theSOD film. In this case, a foaming reaction, in which the resin having ahigh molecular weight is decomposed into substances having a lowmolecular weight such as CH₄, CO₂, H₂ and C by the heat energy in theheat treating step, is brought about within the SOD film so as togenerate a large number of pores within the SOD film, thereby formingthe porous insulating film 14.

[0062] Further, it is possible to use a polymer material in place of theSOD film noted above so as to form the insulating film 14. For example,it is possible to prepare a coating material by mixing a monomer(C_(x)H_(y)) having a high molecular weight, which originally has asporous structure, in a solvent, followed by baking the coated film so asto evaporate the solvent, thereby forming the insulating film 14 havingpores of the molecule level.

[0063] It is also possible to prepare a coating material by mixing anorganic resin having a high thermal stability and another organic resinhaving a low thermal stability. In this case, the organic resin having alow thermal stability is evaporated by the heat energy in the bakingstep so as to form the insulating film 14 having pores.

[0064] Further, it is also possible to prepare a coating material bymixing an inorganic phase of SiO₂ in a polymer material and to apply aheat treatment to the coated film. In this case, the coated film afterthe heat treatment is exposed to an HF atmosphere so as to permitelusion of SiO₂ alone, thereby forming the insulating film 14 havingpores.

[0065] In the manufacturing method shown in FIGS. 5A to 5G, the organicSOD film 31 formed on the wafer 30 is subjected to a heat treatment forconversion into the insulating film 14, followed by selectively etchingthe insulating film 14 so as to permit the insulating film 14 to be leftunremoved in the central portion alone of each chip.

[0066] In the manufacturing method according to a modification of thefirst embodiment, however, after formation of the organic SOD film 31 inthe step shown in FIG. 5A, energy is selectively imparted to the centralportion of each chip as shown in FIG. 6A. As a result, the centralportion of each chip is heated to 350 to 400° C. so as to bake theparticular portion of the organic SOD film 31, thereby forming theinsulating film 14.

[0067] In the next step, that portion of the organic SOD film 31 towhich energy was not imparted is dissolved in an organic solvent so asto be removed and, thus, the insulating film 14 is left unremoved in thecentral portion alone of each chip, as shown in FIG. 6B. The subsequentsteps are equal to those shown in FIGS. 5D to 5G and, thus, thedescription thereof is omitted. Incidentally, the energy noted above canbe imparted by, for example, the irradiation with a laser beam, theirradiation with an electron beam, or the irradiation with a molecularbeam.

[0068] An LSI chip according to a second embodiment of the presentinvention will now be described with reference to FIGS. 7A and 7B. InFIGS. 7A and 7B, those portions which correspond to the portions shownin FIGS. 4A and 4B are denoted by the same reference numerals so as toavoid the overlapping description, and the description will be given toonly those portions which differ from the portions of the LSI chip shownin FIGS. 4A and 4B.

[0069] The LSI chip shown in FIGS. 7A and 7B also has, for example, athree layer structure including the wiring layers 11, 12 and 13. Each ofthese three wiring layers 11, 12 and 13 is formed of a single kind of aninsulating film, i.e., an organic SOD film, and includes a porousinsulating film 14 a formed in the central portion of the chip and anonporous insulating film 14 b formed in the peripheral portion of thechip.

[0070] The porous insulating film 14 a, which has a low dielectricconstant k of, for example, about 2.1, is low in its mechanicalstrength. On the other hand, the nonporous insulating film 14 b, whichhas a high dielectric constant k of, for example, about 2.7, has amechanical strength higher than that of the insulating film 14 a.

[0071] The insulating film 14 a having metal wirings 15 formed in asurface region is a porous insulating film having a low dielectricconstant k of about 2.1. Since the dielectric constant k of theinsulating film 14 a is low, the degree of the capacitive couplingbetween the metal wirings 15 of the adjacent wiring layers is low so asto make it possible to suppress the value of the parasitic capacitanceaccompanying the metal wirings 15 to a small value. As a result, thedelay time of the signal propagated through each of the metal wirings 15can be improved so as to increase the operating speed of the LSI chip.

[0072] On the other hand, the insulating film 14 b positioned around andbelow the bonding pad 17 in each of the wiring layers 11, 12 and 13 is anonporous insulating film. The insulating film 14 b is superior to theinsulating film 14 a in the mechanical strength. Therefore, theinsulating film 14 b is unlikely to be broken even if a mechanicalimpact is applied to the bonding pad 17 in the bonding step for bondinga wire to the bonding pad 17 in the uppermost wiring layer 13 or in thepackaging step.

[0073] As described above, the operating speed of the LSI chip accordingto the second embodiment of the present invention can also be improvedlike the operating speed of the LSI chip shown in FIGS. 4A and 4B.

[0074] In the LSI chip shown in FIGS. 7A and 7B, the insulating filmconstituting each wiring layer is formed of two kinds of insulatingfilms. Alternatively, it is possible for the insulating filmconstituting each wiring layer to be formed of three or more kinds ofinsulating films.

[0075] The LSI chip shown in FIGS. 7A and 7B can be manufactured by themanufacturing method described in the following with reference to FIGS.8A to 8F.

[0076] In the first step, an organic SOD film 31 is formed on a wafer(substrate) 30 having elements and other wiring layers formed therein inadvance by coating the surface of the wafer 30 with a coating materialprepared by mixing an insulating film precursor including SiO₂ having anOH group attached thereto as a basic skeletal structure and a solvent,as shown in FIG. 8A. A spin coating method is employed for the coating.

[0077] In the next step, a heat treatment is applied to the organic SODfilm 31 under an oxygen gas atmosphere or a nitrogen gas atmosphere soas to bring about a crosslinking reaction over the entire region and,thus, to convert the organic SOD film 31 into an insulating film 14 b,as shown in FIG. 8B. In this step, the insulating film 14 b has adielectric constant k of about 2.7.

[0078] In the next step, energy is selectively imparted to theinsulating film 14 b in the central portion of each chip, as shown inFIG. 8C. Since the insulating film 14 b is heated in this step at atemperature higher than the temperature in the previous baking step, thecrosslinking reaction is promoted in the central portion of the chip,with the result that the insulating film 14 b in the central portion ofthe chip is converted into a porous insulating film 14 a having a largenumber of pores. Also, the nonporous insulating film 14 b is leftunchanged in the peripheral portion of the chip.

[0079] The energy noted above can be imparted by, for example, theirradiation with a laser beam, the irradiation with an electron beam orthe irradiation with a molecular beam.

[0080] As a result, formed is an insulating film including theinsulating film 14 a formed in the central portion of the chip and theinsulating film 14 b formed in the peripheral portion of the chip, asshown in FIG. 8D.

[0081] In the subsequent steps, the metal wirings 15 are formed in asurface region of the insulating film 14 a and the bonding pad 17 isformed in a surface region of the insulating film 14 b, as shown inFIGS. 8E and 8F, as in FIGS. 5F and 5G referred to previously.

[0082] In the second embodiment of the present invention describedabove, energy is selectively applied to the insulating film 14 b in thecentral portion of each chip so as to promote a crosslinking reactionand, thus, to form the porous insulating film 14 having a large numberof pores. Alternatively, it is also possible to mix a resin having ahigh molecular weight in the SOD film and to impart energy selectivelyto the SOD film. In this case, a foaming reaction, in which the resinhaving a high molecular weight is decomposed into substances having alow molecular weight such as CH₄, CO₂, H₂ and C by the imparted energy,is brought about within the SOD film so as to generate a large number ofpores within the SOD film, thereby forming the porous insulating film 14a.

[0083] In the method shown in FIGS. 8A to 8F, energy is selectivelyimparted to the insulating film 14 b by, for example, the irradiationwith a laser beam, the irradiation with an electron beam, or theirradiation with a molecular beam so as to bring about a crosslinkingreaction or a foaming reaction, thereby forming the porous insulatingfilm 14 a.

[0084] The porous insulating film 14 a can be formed by another method.Specifically, after formation of the wirings in a surface region of theinsulating film constituting the wiring layer, an alternating-currentmagnetic field is applied to the insulating film so as to generate aneddy current in the wiring and, thus, to increase the temperature of thewiring. As a result, heat is imparted to only that portion of theinsulating film which is positioned in the vicinity of the wiring so asto selectively bring about a crosslinking reaction or a foamingreaction, thereby converting the particular portion of the insulatingfilm into a porous insulating film.

[0085]FIGS. 9A and 9B are a plan view and a cross sectional view,respectively, showing an LSI chip according to a third embodiment of thepresent invention, in which a porous insulating film is formed byapplying an alternating-current magnetic field from the outside asdescribed above. In FIGS. 9A and 9B, those portions which correspond tothe portions shown in FIGS. 4A and 4B are denoted by the same referencenumerals so as to avoid the overlapping description, and the descriptionwill be given to only those portions which differ from the portions ofthe LSI chip shown in FIGS. 4A and 4B.

[0086] As shown in FIGS. 9A and 9B, the metal wirings 15 are formed in asurface region of the nonporous insulating film 14 b after the bakingstep. Then, an eddy current is generated by applying an alternatingcurrent-magnetic field from the outside so as to elevate the temperaturearound the metal wirings 15. As a result, heat is imparted to only thatportion of the insulating film which is positioned in the vicinity ofthe metal wirings 15 so as to selectively bring about a crosslinkingreaction or a foaming reaction, thereby forming the porous insulatingfilm 14 a.

[0087]FIG. 10 is a cross sectional view showing an LSI chip according toa third embodiment of the present invention. Incidentally, In FIG. 10,those portions which correspond to the portions shown in FIG. 4B aredenoted by the same reference numerals so as to avoid the overlappingdescription, and the description will be given to only those portionswhich differ from the portions of the LSI chip shown in FIG. 4B.

[0088] As shown in FIG. 10, a plurality of wiring layers, e.g., threewiring layers 11, 12 and 13, are formed in the LSI chip. It should benoted that two different kinds of insulating films are formed in each ofthese three wiring layers 11, 12 and 13. To be more specific, a porousinsulating film 40 a made of an organic SOD film having a dielectricconstant k of about 2.1 is formed in the region where the metal wirings15 are formed in a surface region. On the other hand, an insulating film40 b made of aluminum oxide (Al₂O₃) is formed in the regions where thebonding pad 17 is formed in a surface region and where a MIM capacitor41 is formed.

[0089] The MIM capacitor 41 comprises an upper electrode, a lowerelectrode, and a capacitor insulating film interposed between the upperelectrode and the lower electrode. The capacitor insulating film isformed of, for example, SiN (silicon nitride), TaO (tantalum oxide), orTiN (titanium nitride).

[0090] The insulating film 40 a having the metal wirings 15 formed in asurface region is a porous insulating film having a small dielectricconstant k of about 2.1. Since the dielectric constant k of theinsulating film 40 a is low, the degree of the capacitive couplingbetween the metal wirings 15 of the adjacent wiring layers is low so asto make it possible to suppress the value of the parasitic capacitanceaccompanying the metal wirings 15 to a small value. As a result, thedelay time of the signal propagated through each of the metal wirings 15can be improved so as to increase the operating speed of the LSI chip.

[0091] On the other hand, the insulating film 40 b made of Al₂O₃ andhaving the bonding pad 17 and the MIM capacitor 41 formed thereinexhibits an excellent mechanical strength, and the amount of thehydrogen gas released when the insulating film 40 b is heated isrelatively small. It follows that the insulating film 40 b is unlikelyto be broken when a mechanical impact is applied to the bonding pad 17in the bonding step for bonding a wire to the bonding pad 17 and in thepackaging step.

[0092] As described above, the insulating film 40 b made of Al₂O₃ isformed in the region where the MIM capacitor 41, etc. are formed.Therefore, in the heating step, the capacitor insulating film of the MIMcapacitor is unlikely to be exposed to the hydrogen gas so as to preventthe deterioration in the performance of the MIM capacitor.

[0093] In the third embodiment described above, an insulating film,which releases a relatively small amount of a hydrogen gas when theinsulating film is heated, is formed in the region where the MIMcapacitor 41 is formed. However, in an LSI chip in which another elementhaving a capacitor insulating film, e.g., a ferroelectric memory, isformed, the insulating film made of Al₂O₃ should be formed in the regionwhere the ferroelectric memory is formed.

[0094] In the third embodiment described above, an insulating film madeof Al₂O₃ is used as an insulating film that releases a hydrogen gas in arelatively small amount. Alternatively, it is also possible to use aSiO₂ film formed by, for example, a plasma CVD method as the insulatingfilm 40 b.

[0095] In the embodiment shown in FIG. 10, the insulating filmconstituting each of the wiring layer is formed of two different kindsof insulating films. However, it is also possible for the insulatingfilm constituting each wiring layer to be formed of three or moredifferent kinds of insulating films.

[0096] In each of the embodiments described above, the different kindsof the insulating films used for forming the same wiring layer are notlimited to those described above. It is possible to use suitableinsulating films depending on the characteristics of the regions withinthe LSI chip. For example, it is possible for the insulating film to beformed of a porous/nonporous organic SOD, MSQ (methyl-silsesquioxane),HSQ (hydrogen-silsesquioxane), SiN, SiON, SiCN, SiO₂, PSG, a polymermaterial-based porous MSX (methyl-poly-siloxane) and a porous PAE(poly-arylene-ether).

[0097] Also, in forming two different kinds of insulating films in eachwiring layer, it is possible to arrange one insulating film 50 in amesh-like arrangement and to arrange another insulating film 51 in anisland-like arrangement, as shown in FIGS. 11A and 11B. It should benoted that the insulating film 50 corresponds to the insulating film 14shown in FIGS. 4A and 4B, which is included in the LSI chip according tothe first embodiment of the present invention. In other words, theinsulating film 50 is porous and has a dielectric constant fallingwithin a range of between 2.2 and 2.7. On the other hand, the insulatingfilm 51 shown in FIGS. 11A and 11B corresponds to the insulating film 16shown in FIGS. 4A and 4B and, thus, is excellent in its mechanicalstrength. Incidentally, it is also possible for the insulating films 50and 51 shown in FIGS. 11A and 11B to correspond to the insulating films16 and 14 shown in FIGS. 4A and 4B, respectively, which is opposite tothat described above.

[0098] In each of the embodiments described above, the technical idea ofthe present invention is applied to an LSI chip including a bonding padas an electrode to which a mechanical pressure is applied.Alternatively, it is also possible to apply the technical idea of thepresent invention to an LSI chip for BGA, in which a large number ofball electrodes are formed in the chip. To be more specific, amechanical impact (mechanical pressure) is applied to the ballelectrodes in the connecting step of the electrodes for mounting the LSIchip for BGA. Therefore, an insulating film having a high mechanicalstrength, e.g., a SiN film formed by a plasma CVD method, is formed inthe region of the wiring layer where the ball electrodes are formed, andan insulating film having a low dielectric constant, e.g., an organicSOD film, is formed in that region of the wiring layer which does notrequire a high mechanical strength like the region where the metalwiring is formed.

[0099] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the present invention in itsbroader aspects is not limited to the specific details andrepresentative embodiments shown and described herein. Accordingly,various modifications may be made without departing from the spirit orscope of the general inventive concept as defined by the appended claimsand their equivalents.

What is claimed is:
 1. A semiconductor device of a multi-wiringstructure, comprising: an electrode to which is applied a mechanicalpressure; a first insulating film formed in a region where it isnecessary to have a high mechanical strength and having said electrodeformed therein; a second insulating film formed in the same layer as thelayer of said first insulating film and formed in a region where amechanical strength higher than that of said first insulating layer isnot required; and a wiring layer formed on the surface of said secondinsulating film.
 2. The semiconductor device according to claim 1,wherein the electrode to which said mechanical pressure is applied is abonding pad, and said first insulating film is formed around or belowsaid bonding pad.
 3. The semiconductor device according to claim 1,wherein said first insulating film is formed in a peripheral portion ofthe semiconductor device.
 4. The semiconductor device according to claim1, wherein said second insulating film has a dielectric constant k nothigher than
 3. 5. The semiconductor device according to claim 1, whereinsaid first insulating film is an SOD film, and said second insulatingfilm is a plasma CVD film.
 6. A semiconductor device of a multi-wiringstructure, comprising: an electrode to which a mechanical pressure isapplied; a nonporous insulating film formed in a region where it isnecessary to have a high mechanical strength and having said electrodeformed therein; a porous insulating film formed in the layer same assaid nonporous insulating film and formed in a region where it isunnecessary to have a mechanical strength equal to that of said firstinsulating film; and a wiring layer formed in a surface region of saidporous insulating film.
 7. The semiconductor device according to claim6, wherein each of said porous insulating film and said nonporousinsulating film is formed of an SOD film.
 8. The semiconductor deviceaccording to claim 6, wherein the electrode to which said mechanicalpressure is applied is a bonding pad, and said nonporous insulating filmis formed around and below said bonding pad.
 9. The semiconductor deviceaccording to claim 6, wherein said nonporous insulating film is a plasmaCVD film, and said porous insulating film is an SOD film.
 10. Asemiconductor device having a multi-wiring structure, comprising: afirst insulating film, which is formed in a first region in which acapacitor insulating film is formed, and releases a relatively smallamount of a gas when heated; and a second insulating film formed in thelayer same as said first insulating film and formed in a second regionother than said first region.
 11. The semiconductor device according toclaim 10, wherein said second insulating film is an insulating film thatrelease a gas when heated in an amount larger than that released by saidfirst insulating film.
 12. The semiconductor device according to claim10, wherein said first insulating film is selected from the groupconsisting of an aluminum oxide film and a plasma CVD oxide film.
 13. Amethod of manufacturing a semiconductor device having a multi-wiringstructure, comprising: coating a substrate with a film of an insulatingmaterial in which a crosslinking reaction or a foaming reaction isgenerated; subjecting the film of said insulating material to a heattreatment so as to bring about a crosslinking reaction or a foamingreaction, thereby forming a first insulating film on said substrate;selectively removing said first insulating film such that said firstinsulating film is selectively left unremoved on said substrate and isremoved in the other region; and forming a second insulating film in theregion where said first insulating film has been removed.
 14. A methodof manufacturing a semiconductor device having a multi-wiring structure,comprising: coating a substrate with a film of an insulating material inwhich a crosslinking reaction or a foaming reaction is generated;imparting energy to the film of said insulating material so as toselectively bring about a crosslinking reaction or a foaming reaction;removing the film of said insulating film in a region in which acrosslinking reaction or a foaming reaction has not taken place andleaving the film of said insulating material unremoved in a region inwhich a crosslinking reaction or a foaming reaction has taken place soas to form a first insulating film on said substrate; and forming asecond insulating film in the region where the film of said insulatingfilm has been removed.
 15. The method of manufacturing a semiconductordevice according to claim 14, wherein said energy is imparted to thefilm of said insulating material by means of irradiation with a laserlight.
 16. The method of manufacturing a semiconductor device accordingto claim 14, wherein said energy is imparted to the film of saidinsulating material by means of irradiation with an electron beam. 17.The method of manufacturing a semiconductor device according to claim14, wherein said energy is imparted to the film of said insulatingmaterial by means of irradiation with a molecular beam.
 18. The methodof manufacturing a semiconductor device according to claim 14, whereinthe film of said insulating material is an organic SOD film.
 19. Amethod of manufacturing a semiconductor device having a multi-wiringstructure, comprising: forming on a substrate an insulating film of aninsulating material in which a crosslinking reaction or a foamingreaction is generated; selectively forming a wiring in a surface regionof said insulating film; and applying an alternating-current magneticfield so as to generate an eddy current in said wiring, thereby heatingsaid wiring so as to selectively bring about a crosslinking reaction ora foaming reaction in that region of said insulating film which ispositioned in the vicinity of said wiring.
 20. The method ofmanufacturing a semiconductor device according to claim 19, wherein saidinsulating film is an organic SOD film.